Advanced Interconnects for ULSI Technology by Mikhail Baklanov, Paul S. Ho, Ehrenfried Zschech

By Mikhail Baklanov, Paul S. Ho, Ehrenfried Zschech

Discovering new fabrics for copper/low-k interconnects is necessary to the ongoing improvement of desktop chips. whereas copper/low-k interconnects have served good, taking into consideration the production of extremely huge Scale Integration (ULSI) units which mix over one thousand million transistors onto a unmarried chip, the elevated resistance and RC-delay on the smaller scale has develop into a major factor affecting chip functionality.

Advanced Interconnects for ULSI Technology is devoted to the fabrics and techniques that can be appropriate replacements. It covers a wide variety of subject matters, from actual rules to layout, fabrication, characterization, and alertness of latest fabrics for nano-interconnects, and discusses:

  • Interconnect services, characterisations, electric homes and wiring necessities
  • Low-k fabrics: basics, advances and mechanical  houses
  • Conductive layers and limitations
  • Integration and reliability together with mechanical reliability, electromigration and electric breakdown
  • New techniques together with 3D, optical, instant interchip, and carbon-based interconnects

Intended for postgraduate scholars and researchers, in academia and undefined, this ebook presents a serious assessment of the allowing know-how on the center of the longer term improvement of computing device chips.

Chapter 1 Low?k fabrics: contemporary Advances (pages 1–33): Geraud Dubois and Willi Volksen
Chapter 2 Ultra?Low?k by means of CVD: Deposition and Curing (pages 35–77): Vincent Jousseaume, Aziz Zenasni, Olivier Gourhant, Laurent Favennec and Mikhail R. Baklanov
Chapter three Plasma Processing of Low?k Dielectrics (pages 79–128): Hualiang Shi, Denis Shamiryan, Jean?Francois de Marneffe, Huai Huang, Paul S. Ho and Mikhail R. Baklanov
Chapter four rainy fresh purposes in Porous Low?k Patterning methods (pages 129–171): Quoc Toan Le, man Vereecke, Herbert Struyf, Els Kesters and Mikhail R. Baklanov
Chapter five Copper Electroplating for On?Chip Metallization (pages 173–191): Valery M. Dubin
Chapter 6 Diffusion limitations (pages 193–234): Michael Hecker and Rene Hubner
Chapter 7 technique Integration of Interconnects (pages 235–265): Sridhar Balakrishnan, Ruth mind and Larry Zhao
Chapter eight Chemical Mechanical Planarization for Cu–Low?k Integration (pages 267–289): Gautam Banerjee
Chapter nine Scaling and Microstructure results on Electromigration Reliability for Cu Interconnects (pages 291–337): Chao?Kun Hu, Rene Hubner, Lijuan Zhang, Meike Hauschildt and Paul S. Ho
Chapter 10 Mechanical Reliability of Low?k Dielectrics (pages 339–367): Kris Vanstreels, Han Li and Joost J. Vlassak
Chapter eleven electric Breakdown in complex Interconnect Dielectrics (pages 369–434): Ennis T. Ogawa and Oliver Aubel
Chapter 12 3D Interconnect expertise (pages 435–490): John U. Knickerbocker, Lay Wai Kong, Sven Niese, Alain Diebold and Ehrenfried Zschech
Chapter thirteen Carbon Nanotubes for Interconnects (pages 491–502): Mizuhisa Nihei, Motonobu Sato, Akio Kawabata, Shintaro Sato and Yuji Awano
Chapter 14 Optical Interconnects (pages 503–542): Wim Bogaerts
Chapter 15 instant Interchip Interconnects (pages 543–563): Takamaro Kikkawa

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Here dielectric damage appears to dominate with only limited pore-sealing success. Whereas these two modifications address the issue of smooth sidewalls for optimum barrier metal deposition, they do not consider the plasma damage to the ILD from etch and strip processes. Although strip (resist removal) damage can be minimized with the use of hardmasks (the lithographic pattern is first transferred to the hardmask, which allows a PR strip without exposing the ILD) [29, 30, 102–105], plasma damage arising from the actual ILD etch cannot be neglected.

Firstly, the increased, accessible surface area of the porous network constitutes a new weakness with regard to plasma-induced damage and wet chemistry processes. Secondly, the decrease in network connectivity as compared to silica and the reduction of density strongly impact the dielectric insulator mechanical properties. 2. It should be mentioned that these trends are qualitative in nature only. Nevertheless, they clearly demonstrate the ever-growing challenges in successfully building advanced semiconductor structures with increased performance and good reliability.

Potential drawbacks to this approach present themselves in the introduction of new material interfaces and the need to remove the additional material at the via bottom. indd 14 12/20/2011 12:45:56 PM Low-k Materials: Recent Advances 15 the former could give rise to interfacial adhesion issues, while the latter could adversely affect the cap-open step to establish metal contact. The second pathway to pore sealing is by plasma modification. Proper selection of a suitable plasma may densify the outermost surface of the via and line sidewalls, enabling deposition of thin, continuous barrier layers [96–101].

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