Analysis and Design of Resilient VLSI Circuits: Mitigating by Rajesh Garg

By Rajesh Garg

This booklet is inspired via the demanding situations confronted in designing trustworthy integratedsystems utilizing glossy VLSI strategies. The trustworthy operation of built-in Circuits (ICs) has turn into more and more tough to accomplish within the deep sub-micron (DSM) period. With continually reducing machine characteristic sizes, mixed with decrease provide voltages and better working frequencies, the noise immunity of VLSI circuits is reducing alarmingly. hence, VLSI circuits have gotten extra prone to noise results resembling crosstalk, energy provide adaptations and radiation-induced delicate errors.

This e-book describes the layout of resilient VLSI circuits. It offers algorithms to research the damaging results of radiation particle moves and processing adaptations at the electric habit of VLSI circuits, in addition to circuit layout options to mitigate the impression of those problems.

  • Describes the state-of-the-art within the parts of radiation tolerant circuit layout and technique version tolerant circuit design;
  • Presents analytical ways to check successfully the severity of electric results of radiation/process diversifications, in addition to recommendations to lessen the consequences because of those problems;
  • Distills content material orientated towards nuclear engineers into modern algorithms and methods that may be understood simply and utilized by means of VLSI designers.

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3 Proposed Analytical Model for the Pulse Width of Radiation-induced Voltage Glitch 25 PTM [7] model card with VDD D 1 V. The radiation-induced transient are classified into four cases, in Sect. 2. The proposed model for the pulse width computation, based on these cases, is introduced in Sect. 3. 4 provides the derivation of the expression for the pulse width of the radiation-induced voltage glitch. 1 Radiation Particle Strike at the Output of an Inverter Consider an inverter INV1 driving three identical inverters as shown in Fig.

H. Chang and S. S. Sapatnekar, “Statistical timing analysis under spatial correlations,” IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems, vol. 24, no. 9, pp. 1467–1482, Sept. 2005. 26. L. He, A. B. Kahng, K. H. Tam, and J. Xiong, “Simultaneous buffer insertion and wire sizing considering systematic CMP variation and random Leff variation,” Proc. of the Intl. Conf. on Computer-Aided Design, vol. 26, no. 5, pp. 845–857, May 2007. 27. K. Cao, S. Dobre, and J. Hu, “Standard cell characterization considering lithography induced variations,” in Proc.

References 1. T. May and M. Woods, “Alpha-particle-induced soft errors in dynamic memories,” IEEE Transaction on Electron Devices, vol. ED-26, pp. 2–9, Jan 1979. 2. J. Pickle and J. Blandford, “CMOS RAM cosmic-ray-induced error rate analysis,” IEEE Transactions on Nuclear Science, vol. NS-29, pp. 3962–3967, 1981. 3. W. Massengill, M. Alles, and S. Kerns, “SEU error rates in advanced digital CMOS,” in Proc. of the European Conf. on Radiation and Its Effects on Components and Systems, Sep. 1993, pp.

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